This invention relates a liquid crystal display device, and more particularly to a technique which is effectively applied to a circuit for supplying a video signal voltage to each pixel.
The active-matrix type liquid crystal display device having an active element for each pixel (for example, a thin film transistor) and switching the active elements has been used widely as a display device of a notebook personal computer.
TFT (Thin Film Transistor) type liquid crystal display module has been known as one of the active-matrix type liquid crystal display device. In a TFT type liquid crystal display module, since a video signal voltage (a gray scale voltage) is applied to a pixel electrode through a thin film transistor (TFT), the TFT type liquid crystal display module is free from crosstalk, and it is possible that the TFT type liquid crystal display module provides a multi-gray scale display without using a special driving method, unlike a simple matrix type liquid crystal display device, which requires a special driving method for preventing crosstalk between pixels.
As a method for applying a multi-gray scale video signal voltage to each pixel to render an active-matrix type liquid crystal display device capable of the multi-gray scale display, a method described in Japanese Published Unexamined Patent Application No. Hei 5-35200 (published on Feb. 12, 1999) (corresponding to U.S. Pat. No. 5,337,070, issued on Aug. 9, 1994) has been known.
Japanese Published Unexamined Patent Application No. Hei 5-35200 discloses a method in which 2m voltage bus lines are provided, and gray scale voltages provided from the 2m voltage bus lines vary in a staircase fashion having 2k steps during one horizontal scanning period corresponding to one horizontal scanning line.
One of the above-mentioned 2m voltage bus lines is selected based on the high-order m bits of an n-bit display data, one of the voltage levels is selected from the gray scale voltage varying in a staircase fashion on the selected voltage bus line based on the lower-order k (k=nxe2x88x92m) bits of the n-bit display data, and the selected voltage level is applied to a pixel electrode of each pixel.
For example, a case in which the display data is 3 bits (n=3), m=1, and k=2 is assumed. Two voltage bus lines are provided and each voltage bus line is supplied with a gray scale voltage varying in a staircase fashion having four steps during one horizontal scanning period such that eight voltage levels of the two gray scale voltages are different from each other.
A gray scale voltage carried on one of two voltage bus lines is selected based on the high-order 1 bit of the 3-bit display data, one voltage level is selected from the gray scale voltage varying in a staircase fashion having four steps on the selected voltage bus line, based on the lower-order 2 bits of the 3-bit display data, and the selected voltage level is applied to the pixel electrode of each pixel.
According to the driving method described in the above-mentioned publication, the operating speed of the circuit for applying a video signal voltage on each pixel can be reduced, and the number of voltage bus lines can be reduced.
Recently, the liquid crystal display device has been increased in the number of steps of the gray scales to 64 or 256.
In the case where gray scales of 64 or 256 steps is realized by the method described in Japanese Published Unexamined Patent Application No. Hei 5-35200, the circuit scale of a selector circuit for selecting voltage levels varying in a staircase fashion having 2k steps on the selected voltage bus lines should be large. In the case where the selector circuit is incorporated into a liquid crystal display panel, an area occupied by the selector circuit should be large, and the liquid crystal display panel should be consequently large. The large size is disadvantageous for the liquid crystal display panel.
The present invention solves the problem of the above-mentioned prior art, and it is the object of the present invention to provide a technique for rendering the circuit scale of the driving means for horizontal scanning of a liquid crystal display device small.
The above-mentioned object and novel features of the present invention will be obvious with reference to the description of the specification and the accompanying drawings.
In accordance with one embodiment of the present invention, there is provided a liquid crystal display device having a pair of opposing substrates at least one of which is transparent and a liquid crystal layer sandwiched between the pair of opposing substrates comprising: a plurality of video signal lines, a plurality of scanning signal lines perpendicular to the plurality of video signal lines, a plurality of pixels arranged in a matrix and each surrounded by two adjacent video signal lines among the plurality of video signal lines and by two adjacent scanning signal lines among the plurality of scanning signal lines, each of the plurality of video signal lines being connected to pixels among the plurality of pixels arranged in a same column of the matrix via a respective switching element, each of the plurality of scanning signal lines being connected to the switching elements of pixels among the plurality of pixels arranged in a same row of the matrix, a video signal line drive circuit for supplying video signal voltages to each of the plurality of video signal lines, a power supply for supplying 2M gray scale voltages varying with a horizontal scanning period to the video signal line drive circuit, and a display control circuit for controlling the video signal line drive circuit, wherein the display control circuit supplies display data of at least N bits and P kinds of time control signals varying with the horizontal scanning period to the video signal line drive circuit, the video signal line drive circuit includes: memory for storing the display data of at least N bits, a plurality of selector circuits each associated with a respective one of the plurality of video signal lines, for selecting one of the 2H gray scale voltages in accordance with M bits of the display data of at least N bits, a plurality of switching circuits each associated with a respective one of the plurality of video signal lines, and each comprising P switching elements, the P switching elements each being supplied with a respective one of the P kinds of time control signals and a first fixed voltage, for selecting one of the respective one of the P kinds of time control signals and the first fixed voltage in accordance with a corresponding one of Q bits other than the M bits, of the display data of at least N bits, the first fixed voltage being in common for all of the P switching elements, the P kinds of time control signals comprising such pulses as to uniquely determine a time represented by the Q bits of the display data based upon the Q bits of the display data, a plurality of logic circuits each associated with a respective one of the plurality of video signal lines, each being supplied with the selected ones of the respective one of the P kinds of time control signals and the first fixed voltage from the P switching elements, and each being configured so as to change state when all of the selected ones of the respective one of the P kinds of time control signals and the first fixed voltage are the first fixed voltage, and a plurality of output circuits each associated with a respective one of the plurality of video signal lines, each being configured so as to supply a voltage level of the selected one of the 2M gray scale voltages at an instant when a corresponding one of the plurality of logic circuits changes state, to a corresponding one of the plurality of video signal lines.
In accordance with another embodiment of the present invention, there is provided a liquid crystal display device having a pair of opposing substrates at least one of which is transparent and a liquid crystal layer sandwiched between the pair of opposing substrates comprising: a plurality of video signal lines, a plurality of scanning signal lines perpendicular to the plurality of video signal lines, a plurality of pixels arranged in a matrix and each surrounded by two adjacent video signal lines among the plurality of video signal lines and by two adjacent scanning signal lines among the plurality of scanning signal lines, each of the plurality of video signal lines being connected to pixels among the plurality of pixels arranged in a same column of the matrix via a respective switching element, each of the plurality of scanning signal lines being connected to the switching elements of pixels among the plurality of pixels arranged in a same row of the matrix, a video signal line drive circuit for supplying video signal voltages to each of the plurality of video signal lines, a power supply for supplying a gray scale voltage varying with a horizontal scanning period to the video signal line drive circuit, and a display control circuit for controlling the video signal line drive circuit, wherein the display control circuit supplies display data of at least N bits and N kinds of time control signals varying with the horizontal scanning period to the video signal line drive circuit, the video signal line drive circuit includes: memory for storing the display data of at least N bits transmitted from the display control circuit, a plurality of switching circuits each associated with a respective one of the plurality of video signal lines, and each comprising N switching elements, the N switching elements each being supplied with a respective one of the N kinds of time control signals and a first fixed voltage, for selecting one of the respective one of the N kinds of time control signals and the first fixed voltage in accordance with a corresponding one of N bits of the display data of at least N bits, the first fixed voltage being in common for all of the N switching elements, the N kinds of time control signals comprising such pulses as to uniquely determine a time represented by the N bits of the display data based upon the N bits of the display data, a plurality of logic circuits each associated with a respective one of the plurality of video signal lines, each being supplied with the selected ones of the respective one of the N kinds of time control signals and the first fixed voltage from the N switching elements, and each being configured so as to change state when all of the selected ones of the respective one of the N kinds of time control signals and the first fixed voltage are the first fixed voltage, and a plurality of output circuits each associated with a respective one of the plurality of video signal lines, each being configured so as to supply a voltage level of the gray scale voltage at an instant when a corresponding one of the plurality of logic circuits changes state, to a corresponding one of the plurality of video signal lines.
In accordance with another embodiment of the present invention, there is provided a liquid crystal display device having a pair of opposing substrates at least one of which is transparent and a liquid crystal layer sandwiched between the pair of opposing substrates comprising: a plurality of video signal lines disposed on one of the substrates, a plurality of scanning signal lines perpendicular to the plurality of video signal lines and disposed on the one of the substrates, a plurality of pixels arranged in a matrix and each surrounded by two adjacent video signal lines among the plurality of video signal lines and by two adjacent scanning signal lines among the plurality of scanning signal lines, each of the plurality of video signal lines being connected to pixels among the plurality of pixels arranged in a same column of the matrix via a respective switching element, each of the plurality of scanning signal lines being connected to the switching elements of pixels among the plurality of pixels arranged in a same row of the matrix, a video signal line drive circuit for supplying video signal voltages to each of the plurality of video signal lines, a plurality of display data lines for supplying display data to the video signal line drive circuit, and at least one gray scale voltage line each for supplying a gray scale voltage varying with a horizontal scanning period to the video signal line drive circuit, wherein the video signal line drive circuit includes: a plurality of display data processing circuits each associated with and disposed adjacent to a respective one of the plurality of display data lines, a plurality of gray scale voltage output circuits each associated with a respective one of the plurality of video signal lines for outputting a voltage level of the gray scale voltage varying with the horizontal scanning period, at an instant determined by the plurality of display data processing circuits based upon the display data, to a corresponding one of the plurality of video signal lines, and the plurality of display data processing circuits associated with a respective one of the plurality of video signal lines and a corresponding one of the plurality of gray scale voltage output circuits are cascaded in this order.
In accordance with another embodiment of the present invention, there is provided a liquid crystal display device having a pair of opposing substrates at least one of which is transparent and a liquid crystal layer sandwiched between the pair of opposing substrates comprising: a plurality of video signal lines disposed on one of the substrates, a plurality of scanning signal lines perpendicular to the plurality of video signal lines and disposed on the one of the substrates, a plurality of pixels arranged in a matrix and each surrounded by two adjacent video signal lines among the plurality of video signal lines and by two adjacent scanning signal lines among the plurality of scanning signal lines, each of the plurality of video signal lines being connected to pixels among the plurality of pixels arranged in a same column of the matrix via a respective switching element, each of the plurality of scanning signal lines being connected to the switching elements of pixels among the plurality of pixels arranged in a same row of the matrix, a video signal line drive circuit for supplying video signal voltages to each of the plurality of video signal lines, a plurality of display data lines for supplying display data to the video signal line drive circuit, a plurality of storage devices each associated with and disposed adjacent to a respective one of the plurality of display data lines for storing the display data, at least one gray scale voltage line each for supplying a gray scale voltage varying with a horizontal scanning period to the video signal line drive circuit, a plurality of time control signal lines for supplying a plurality of kinds of time control signals varying with the horizontal scanning period to the video signal line drive circuit, the plurality of kinds of time control signals comprising such pulses as to uniquely determine a time represented by the display data based upon the display data, a plurality of display data processing circuits each associated with a respective one of the plurality of video signal lines for determining a time represented by the display data based upon the display data and the plurality of kinds of time control signals, and a plurality of selector circuits each associated with a respective one of the plurality of video signal lines for selecting a voltage level of the gray scale voltage at an instant of time determined by a corresponding one of the plurality of display data processing circuits.
In accordance with another embodiment of the present invention, there is provided a liquid crystal display device having a pair of opposing substrates at least one of which is transparent and a liquid crystal layer sandwiched between the pair of opposing substrates comprising: a plurality of video signal lines disposed on one of the substrates, a plurality of scanning signal lines perpendicular to the plurality of video signal lines and disposed on the one of the substrates, a plurality of pixels arranged in a matrix and each surrounded by two adjacent video signal lines among the plurality of video signal lines and by two adjacent scanning signal lines among the plurality of scanning signal lines, each of the plurality of video signal lines being connected to pixels among the plurality of pixels arranged in a same column of the matrix via a respective switching element, each of the plurality of scanning signal lines being connected to the switching elements of pixels among the plurality of pixels arranged in a same row of the matrix, a video signal line drive circuit for supplying video signal voltages to each of the plurality of video signal lines, N display data lines for supplying N-bit display data to the video signal line drive circuit, a gray scale voltage line for supplying a gray scale voltage varying in a staircase fashion having 2N steps with a horizontal scanning period to the video signal line drive circuit, N time control signal lines for supplying N kinds of time control signals comprising such pulses as to uniquely determine a time represented by the display data based upon the display data, N display data processing circuits each associated with a respective one of the plurality of video signal lines for determining a time represented by the display data based upon the display data and the plurality of kinds of time control signals, the N display data processing circuits each being disposed on an extension line of the respective one of the plurality of video signal lines, and N selector circuits each associated with a respective one of the plurality of video signal lines for selecting and outputting a voltage level of the gray scale voltage at an instant of time determined by a corresponding one of the plurality of display data processing circuits.